The present invention relates to semiconductor fabrication and more particularly, to a structure and method for obtaining a compact cell area in an array comprising vertical MOSFETs formed over a buried bit line conductor, with stacked capacitors formed above the surface of the silicon.
Present trends in DRAM technology are constantly driving towards reduction in minimum feature size and more compact cell layouts. As a result of the need for ever-increasing array densities, the scalability of contemporary planar MOSFET cells using trough storage capacitors for feature sizes equal to 150 nm and smaller is facing fundamental concerns. The main concern with the scalability of the cell MOSFET is the increased p-well doping concentration needed to meet off-current objectives. It is known in the art that increased array well doping concentration may result in a marked increase in array junction leakage, which degrades retention time. The problems of scalability related to the cell MOSFET, by itself, is driving a paradigm shift towards vertical MOSFET access transistors in the array.
Moreover, the majority of DRAM product utilizes stacked capacitor (STC) DRAM technology. As ground rules (minimum feature sizes) are reduced the amount of capacitance available from deep trough storage capacitors decreases. This is a result of limitations on the scalability of the thickness of the node dielectric, limitations on the etch depth of the deep trough, and because of the reduction of capacitance area that occurs with ground rule reduction (scaling) and more dense cell layouts. RIE (reactive ion etching) lag effect caused by the smaller storage trough openings makes etching adequately deep troughes difficult. Aspect ratios of greater than 50:1, for example, can be entailed, and filling of this extremely high aspect ratio presents major difficulties. Furthermore the higher aspect ratios associated with aggressively scaled deep trough capacitors results in increased series resistance, which, in turn, results in greatly decreased signal development within a given time window. Barring any significant developments regarding higher dielectric constant node insulators and trough fill materials having lower resistivity, it is predicted that trough capacitor storage elements may not be practical beyond the 120 nm generation. Therefore, the long-term (100 nm and beyond) prognosis for the favored DRAM storage element appears to be stacked capacitors. Still, significant improvements concerning the leakage and reliability of high dielectric materials (e.g., barium titanate strontium oxidexe2x80x94BTSO) for STC cells must occur before widespread manufacturing is likely. However, because of the popularity of STC DRAM, extensive industry wide resources are being directed to solve the problems associated with BTSO and other high dielectric materials.
Integration of vertical access MOSFETs and stacked capacitors is a challenging task and has not yet been adopted by the industry. As commonly practiced by DRAM manufacturers, word lines, bit lines and stacked capacitors all reside on or above the silicon surface. An arrangement of such on-or-above-surface cell elements with a vertical access transistor complicates forming the connections with the access transistor and occupies more silicon real estate than deep trough capacitor DRAM cells with vertical access MOSFETs.
To further enhance scalability, the use of vertically oriented channels has been proposed for decoupling the channel length of the cell access MOSFET from the minimum lithographic feature size. Only a limited amount of art exists for STC cells with access transistors having some portion of the channel oriented vertically. Within this limited art, the xe2x80x9cU-shapedxe2x80x9d channel has been proposed as a means of building the MOSFET beneath the silicon surface. Other cell elements, including the bit lines, are still arranged above the surface. However, the concavity of the xe2x80x9cU-shapedxe2x80x9d silicon surface with respect to the gate conductor weakens gate control, thereby increasing substrate sensitivity and sub-threshold swing, with accompanying severely decreased available drive current and array performance.
Related art addresses problems associated with increased DRAM density and bit lines arranged above the silicon surface as outlined in the foregoing. Solutions disclosed in the related art include a STC DRAM cell having a bit line buried beneath the surface of the silicon while providing a vertically oriented access transistor. To address problems associated with a Ushaped channel, a channel in the vertically oriented transistor extends in a straight line so that the channel charge carriers flow along a straight-line path from source to drain of the cell access transistor.
However, additional problems associated with STC cells include that cells having an area smaller than 8 F2 (where F is a minimum lithographic feature size) are difficult to fabricate because of the requirement to form both a capacitor contact area and a transistor. Methods exist for forming cell areas smaller than 8 F2, but these typically entail complications in processing that can add to product costs.
The present invention improves on structure and method for semiconductor fabrication described in the related art to efficiently fabricate cells having an area substantially less than 8 F2. According to the present invention, cell areas substantially less than 8 F2 are achieved concurrently with allowing stacked capacitors to be formed above the surface of the silicon, vertically oriented access MOSFETs beneath the silicon surface, and bit line wiring beneath the MOSFETs.
According to an embodiment of the invention, a trough is formed in a semiconductor substrate. A buried bit line is formed in the trough. Preferably, the bit line is completely enclosed by a dielectric liner. A vertical transistor is formed in the substrate above the buried bit line. The gate conductor may be formed in the trough above the buried bit line, with source and drain diffusions spaced along a sidewall of the trough. Isolation regions are formed in the semiconductor substrate to isolate the transistors. Word lines are formed above the surface of the semiconductor substrate in a direction perpendicular to the direction of the buried bit lines. A capacitor contact is formed above the surface of the semiconductor substrate at an area of the active region between adjacent word lines. A stacked capacitor structure may then be formed above the surface of the semiconductor substrate.
In forming the capacitor contact, an active region is formed which is rhomboid in shape when viewed from a plan view. In a preferred embodiment, the rhomboid shape allows a word line pitch substantially equal to 2 F and a bit line pitch substantially equal to 2.5 F in the array, enabling a cell area substantially equal to 5 F2 while still providing enough space for a capacitor contact to be reliably formed in the active region. To form the capacitor contacts, a simple stripe mask may be used. An array cell area of about 5 F2 is thereby enabled in a simplified process as compared to related art.
In a preferred embodiment, the formation of compact, high-density cells as described above may be integrated with the formation of salicided structures in the array support circuitry for improved performance.